The invention relates to a MOS transistor for a photo cell, comprising an active region and an isolating passive region joining the active region, wherein a photosensitive source zone, a drain electrode and a gate electrode are formed on the active region.
It is known from the German Patent 42 09 536 C2 to use such a MOS transistor in a photo cell for a pick-up chip. Such a pick-up chip comprises a plurality of photo cells arranged in two-dimensional arrays, which are each connected to a read-out logic for projection of a high input signal dynamic ratio to a reduced output signal dynamic ratio.
This photo cell is coupled to a read-out logic which is designed for projection of a high input signal dynamic ratio to a reduced output signal dynamic ratio so that a main electrode of a first photosensitive MOS transistor is connected to the gate of a second MOS transistor, that a control voltage is applied to the gate of the first MOS transistor, which serves to control the compression of the input signal dynamic ratio, that the other main electrode of the second MOS transistor is at a common potential, and that an output signal amplifier is connected to the second main electrode of the second MOS transistor.
When the drain electrode and the gate of the first transistor are shorted and connected to a fixed potential a precisely logarithmic output characteristic is achieved over a range of more than seven decades, which characteristic allows for a radiometrically unambiguous evaluation of the information in the picture.
For an improvement of the resolution of an array equipped with such photo cells it is necessary that the photo cell miniaturisation be continued. One method suitable for a further miniaturisation of the transistors of a photo cell is the so-called STI (shallow trench isolation) method wherein the active zones of the transistors are isolated by means of a trench filled with an oxide, with the electrode material for the gate electrode being disposed in strip form across the direction of current flow. The active zone (semiconductor material) is thus framed laterally by two isolating passive zones (oxide), with the gate electrode extending from a passive zone all over the active zone to the other passive zone (cf. Somnath Nag xe2x80x9cShallow trench isolation for sub-0.25 mm IC technologiesxe2x80x9d in: Solid State Technology, 1997, vol. 40, No. 9, pp. 129-135).
Even though this transistor, which is configured by means of the STI method, is fundamentally suitable for use as photosensitive element in the photo cell mentioned by way of introduction, such transistors produced with the STI technique present parasitic transistors at the interfacial regions between the active region and the isolating oxide regions. These parasitic transistors make themselves noticed at the characteristic in the low signal strength range, the so-called xe2x80x9csubthresholdxe2x80x9d range. This part of the characteristic should follow an exponential course if the gate and the drain electrode are connected to the same potential. Due to the parasitic transistors, however, another signal is superimposed on the characteristic having an inherent exponential course, which signal is partly essentially stronger than the signal proper and hence interferes with the exponential course. A transistor manufactured with the STI technique, which can be miniaturized, is therefore not suitable for the photo cell mentioned by way of introduction, on account of these parasitic transistors.
The invention is now based on the problem of providing a MOS transistor for a photo cell, which allows for a further miniaturisation of the photo cell and which is moreover suitable for generating an exponential characteristic of the photo cell.
This problem is solved by a MOS transistor having the features defined in Claim 1. Expedient improvements of the invention are defined in the dependent claims.
Due to the inventive configuration of the MOS transistor, which comprises an annular region following the gate electrode and where the drain electrode or the photosensitive source region, respectively, is disposed within the annular gate electrode, produces the effect that the current flows in a radial direction towards the centre or away from the centre of the annular region of the gate electrode. Thus a flow of current along the transition zone between the active and passive regions is not created so that any parasitic marginal effects are precluded.
The gate electrode comprises an appendix which crosses merely either the active source region or the drain electrode so that it does not take any influence on the characteristic of the inventive MOS transistor. The appendix rather permits the establishment of the electric contact of the gate electrode with an electric conductor above the passive region, as is necessary due to the manufacturing conditions.
With the inventive configuration of the MOS transistor eliminating any parasitic marginal effects, the STI method can be applied for producing it so that the passive isolating regions can be kept very narrow. The inventive MOS transistor is therefore better to miniaturise than comparable conventional transistors and permits the production of photosensitive arrays having a high resolution.
In a preferred embodiment the gate electrode and the drain electrode are connected to the same electrical potential so that the MOS transistor presents a logarithmic characteristic extending over several decades.